MIL-STD-1553 FPGA Network Traffic Emulator

This project uses a Lattice iCE40 Ultra FPGA (iCE5LP2k) to emulate traffic on a MIL-STD-1553 network. It simulates transmissions on the bus and includes messages sent from a BC to a number of different RTs. It also includes the status responses from each of the RTs to the BC. The addresses are configurable, and the data consists of a rolling counter. The output is electrically isolated, providing a degree of protection to both the FPGA and other network devices. The PROM is programmed using a bed-of-nails pogo-pin adapter.

Right-click to open larger images below.


Evaluation prototype

Production version

Programming adapter

Schematic

Oscilloscope capture

Decoded waveform

I also have a similar project that monitors all packets on the network (BM mode) and sends the data to a serial terminal. An example of a typical data capture is shown below, C = command/status packet, and D = data packet.

Last update: 15 Oct 2017
© Steven J. Merrifield